This is a highly-parallel architecture computer - to the point of being a single-bit processor. Naturally, wider-width operations can be built up from iterated single-bit ones.
A single-bit add generates a single bit carry, that is used for the next bit. But wide words take longer to process.
This architecture can perform like fully associative memory which has only specialised chips that use it - it must just be done at one cycle per bit.
I blogged a while back about the basic engine, so lets start there :-
Arithmetic Processing using Associative memory
The SIMD engine hangs off all RAM blocks in the FPGA - of which there are 50, arranged as 1k x 36 - a possible total of 1800 bits wide. However, about four are needed elsewhere.
The SIMD engine has simple bit-serial capabilities - and, or, xor, adc, not. It has a stack, so it can also be thought of as a forth machine, and is programmed in the same file the sequencer.
Let us count the problems…
Data I/O - we have to keep the beast fed. This will be as big a job as the compute, and will probably need its own PE. I haven’t thought a lot about this, other than having dual-port RAM or something. If it is read out the same way as the PEs read the data, it wil also need to be turned through 90 degrees - you read 32 columns, and then you have rows of data to be read out.
The sequencer is based on the J1 forth CPU, by James Bowman. This is a very simple 16 instruction core.
The native RAM blocks inside the Artix7 FPGA are 18 bits wide, so I extended the J1 CPU to 18 bits wide, to provide more code space and wider instructions.
The extra instruction space is used to drive the SIMD bit-serial CPUs. This means SIMD instructions can be mixed freely with J1 instructions. The finished code will have long strings of SIMD instructions with basic loop control and host interaction using J1 instructions.
Wizzy consulting is where Andy Rabagliati hangs out.
A scheme where telephone wire is replaced by Appropriate technology - sneakernet.
Briefly, a USB stick is moved between a location without internet to a place with internet.
When it is plugged in, it picks up and drops off email, acting as a high-latency replacement for the telephone wire.
This scheme is no longer suitable for current uses of email, which include (for instance) the emailing of web links, so I have removed these pages.
I used to have the sources and binaries of the ispy / mtest tools I wrote here, but more modern ones that compile more cleanly can be found on github and also on Geekdot pages
ispy scouts out a transputer network of the T4/T8/T2/C004 family, and reports back processor type, boot link and speed, and connection diagram.
It can also program the C004s in the network, and compare the current network to a reference.